1. Field of the Invention
The present invention relates to a semiconductor assembly. In particular, the present invention relates to a semiconductor assembly with a seal ring disposed in a seal ring region and embedded in a dielectric layer to cover and fill up recesses.
2. Description of the Prior Art
The micro electro mechanical system (MEMS) is a tiny device with both the electronic and mechanical functions. Apart from the traditional electronic and mechanical processing methods, the current micro electro mechanical system is done by micro-processing techniques. The current methods to manufacture the micro electro mechanical system are, for example, silicon-based method, the LIGA method and the polymer method. Considering the cost for the mass production, the well-developed semiconductor process is much favored to manufacture the micro electro mechanical system due to its potential capability.
Because the micro electro mechanical system is a tiny device with both the electronic and mechanical functions, it is naturally very susceptible to the damages of the contaminations, such as impurities, small particles or mechanical stress, from the surroundings. Therefore, a solution is needed to protect the micro electromechanical system from any undesirable damages. In order to protect the fragile and vulnerable parts in the micro electro mechanical system from damages and contaminations from the surroundings, one of the direct solutions is to leave the entire micro electro mechanical system in a hermetically sealed cavity. Such hermetically sealed cavity is called a sealing ring. Currently methods are proposed to form the sealing ring.
U.S. Pat. No. 7,354,799 proposes a method to form the sealing ring. The method for forming such seal ring is, firstly, to directly etch the silicon substrate to form multiple vias for use in anchoring the seal ring by using a patterned photo resist as an etching mask. Secondly, the seal ring is formed on the silicon substrate by a serious of steps, such as the formation of a seed layer, a dielectric layer, a patterned photo resist layer and metal deposition on the silicon substrate. However, in accordance with the method to form the seal ring disclosed in U.S. Pat. No. 7,354,799, i.e. directly etching the silicon substrate to form multiple vias for use in anchoring the seal ring in the silicon substrate, is not a standard operation for the conventional semiconductor process to form vias. In other words, it is not a good solution which is not compatible with the standard semiconductor process.
Since it is widely accepted that the well developed semiconductor process techniques are suitable to manufacture the micro electro mechanical system, the industry surely looks forward to using a method which is compatible with the standard semiconductor process to form the seal ring. The applicant therefore acknowledges the urgent demand to utilize the standard semiconductor process to achieve a breakthrough in forming the seal ring.